1. Field of the Invention
The present invention relates to a nonvolatile memory and its driving method, particularly relates to a nonvolatile memory that enables allowing a reading margin a sufficient value, in which disturbance in writing to a close cell is prevented and that is almost free of a malfunction.
2. Description of the Related Art
For a memory cell where each memory transistor having MFMIS structure which is an example of a semiconductor memory wherein data can be electrically written and data can be stored in a state of no power supply is arrayed in a matrix, 1T/2C memory cell structure composed by one selected transistor and two memory capacitors as shown in FIG. 10 for example is proposed. In this structure, each one electrode of the memory capacitors is connected, is connected to the gate electrode of the selected transistor and each other electrode of the memory capacitors is connected to the source and the drain of the selected transistor. Therefore, there is a problem that source/drain voltage VSD and gate voltage VG cannot be independently set.
In this semiconductor memory, the source of each memory cell on each line in a transverse direction is connected to be a bit line BL1, BL2, - - - and the drain of each memory cell arranged in each column in a longitudinal direction is connected to be a word line WL1, WL2, - - - .
For this memory cell structure, FET having MFMIS structure wherein a metallic layer (M) and an insulator layer (I) intervene between ferroelectrics and semiconductor as a buffer layer as shown in a sectional explanatory drawing in FIG. 11 is proposed. The FET having MFMIS structure is composed by sequentially laminating a gate oxide film 3, a floating-gate 4, a ferroelectric film 5 and a control gate 6 on a channel area formed between source area S and a drain area D of a semiconductor substrate 1.
In this structure, normally, when the semiconductor substrate 1 is installed and positive voltage is applied to the control gate 6 as shown in FIG. 12A, polarization occurs in the ferroelectric film 5. Even if the voltage applied to the control gate 6 is removed, negative charge is generated in a channel formation area by remanent polarization of the ferroelectric film 5. This shall be a state of 1.
Conversely, when negative voltage is applied to the control gate 6, polarization in a reverse direction occurs in the ferroelectric film 5. Even if the voltage applied to the control gate 6 is removed, positive charge is generated in the channel formation area by remanent polarization of the ferroelectric film 5. This shall be a state of 0. As described above, information xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 can be written to FET. FIGS. 12A and 12B respectively show a state in which information xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 is written.
Written information is read by applying reading voltage Vr to the control gate. The reading voltage Vr is set to a value between threshold voltage Vth1 in a state of 1 and threshold voltage Vth0 in a state of 0. It can be discriminated whether written information is 1 or 0 by detecting whether drain current flows or not when reading voltage Vr is applied to the control gate 6.
As described above, according to FET having MFMIS structure, one memory cell can be composed of one device and non-destructive reading can be satisfactorily performed.
Therefore, both can be identified.
However, in case the capacity Cf1 and Cf2 of memory capacitors are sufficiently larger than the capacity COX depending upon a gate insulating film, gate voltage VG normally becomes a half of VSD, relationship between drain current ID and source/drain voltage VSD in writing xe2x80x981xe2x80x99 and in writing xe2x80x980xe2x80x99 are respectively as shown in FIGS. 12A and 12B and in reading, intermediate voltage is required to be set so that these values can be identified. Therefore, as shown in FIG. 13, in case reading voltage Vr is set to a value between the minimum level in writing xe2x80x981xe2x80x99 and the maximum level in writing xe2x80x980xe2x80x99, there is a problem that a reading margin between 1 and 0 is small. Therefore, in the case of a cell to which xe2x80x980xe2x80x99 is written, a coercive electric field may be also exceeded, it is judged that xe2x80x981xe2x80x99 is written to a cell to which xe2x80x980xe2x80x99 should be written and the reverse case occurs.
A nonvolatile memory wherein reliable reading characteristics can be acquired by allowing a reading margin a large value without causing wrong reading is desired.
There is a memory in which memory transistors having such MFMIS structure are arrayed in a matrix. Above all, a memory which is an example of a semiconductor memory in which data can be electrically written and which can store data in a state of no power supply wherein memory transistors having MFMIS structure are arrayed in a matrix is composed by composing one memory cell by one memory transistor and arraying memory cells lengthwise and crosswise as shown in FIG. 14 for example. In this semiconductor memory, the source of each memory cell on each line in a transverse direction is connected to be a source line SL1, SL2, - - - , the drain of each memory cell arranged in each column in a longitudinal direction is connected to be a drain line DL1, DL2, - - - , substrate potential is connected to be a back gate line BL1, BL2, - - - and the control gate of each memory cell arranged on each line in the transverse direction is connected to be a word line WL1, WL2, - - - , WLn.
As for the structure of the memory cell, as shown in sectional explanatory drawings in FIGS. 15A and 15B, FET having MFMIS structure in which a metallic layer (M) and an insulator layer (I) intervene between ferroelectrics and semiconductor as a buffer layer is proposed. The FET having MEMIS structure is composed by sequentially laminating a gate oxide film 105, a floating-gate 106, a ferroelectric film 107 and a control gate 108 on a channel area 104 formed between a source area 102 and a drain area 103 on a semiconductor substrate 101.
In this structure, normally, when the semiconductor substrate 101 is installed and positive voltage is applied to the control gate 108 as shown in FIG. 15A, polarization occurs in the ferroelectric film 107. Even if the voltage applied to the control gate 108 is removed, negative charge is generated in a channel formation area CH by remanent polarization of the ferroelectric film 107.
This shall be a state of 1.
Conversely, when negative voltage is applied to the control gate 108, polarization occurs in the reverse direction in the ferroelectric film 108. Even if the voltage applied to the control gate 108 is removed, positive charge is generated in the channel formation area CH by remanent polarization of the ferroelectric film 108. This shall be a state of 0.
As described above, information xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 can be written to FET.
Reading written information is executed by applying reading voltage Vr to the control gate. The reading voltage Vr is set to a value between threshold voltage Vth1 in a state of 1 and threshold voltage Vth0 in a state of 0. It can be discriminated by detecting whether drain current flows or not when the reading voltage Vr is applied to the control gate 108 whether written information is 1 or 0.
As described above, according to the FET having MFMIS structure, one memory cell can be composed by one device and non-destructive reading can be satisfactorily performed.
However, when a selected cell is set to a writing state as described above in writing data to the selected cell, an adjacent cell on the same line shares the source line SL and the word line WL of the corresponding cell and an adjacent cell in the same column shares the back gate line BL and the drain line DL. Therefore, also in an unselected cell, VF=VC to ⅓ of VC, a coercive electric field may be exceeded, writing is executed to a cell to be not written and the reverse case occurs.
Then, the provision of a nonvolatile memory wherein reliable writing characteristics can be acquired without causing wrong reading in a memory cell array is desired.
A first aspect of the invention provides a nonvolatile memory wherein reliable reading characteristics can be acquired without causing wrong reading by allowing a reading margin a large value.
A second aspect of the invention provides a nonvolatile memory wherein reliable writing characteristics can be acquired without causing wrong writing in a memory cell array.
The first aspect of the invention is characterized in that a control gate is connected to a word line, a source area is connected to a source line, a drain area is connected to a drain line, a floating line composed of writing gates and composed so that a capacitor is formed between the floating line and the floating-gate is provided, the word line and the source line on the same line in a matrix are connected in common, the drain line and the floating line in the same column in the matrix are connected in common and source/drain voltage and gate voltage can be independently set in a nonvolatile memory wherein transistors having MFMIS structure composed by sequentially laminating a floating-gate, a ferroelectric layer and a control gate via a gate insulating film on the surface between a source area and a drain area respectively formed on a semiconductor substrate are arrayed in the matrix.
Also, the second aspect of the invention is characterized in that one memory cell composes FET having MFMIS structure acquired by sequentially laminating a floating-gate, a ferroelectric layer and a control gate via a gate insulating film on the surface between a source area and a drain area respectively formed on a semiconductor substrate, the floating-gate is extended on an element isolation insulating film, the floating-gate is provided with a capacitor insulating film between the floating-gate and a writing gate formed on the element isolation insulating film and composes a capacitor.
As in such an MFMIS transistor, source/drain voltage and gate voltage can be independently set, a nonvolatile memory wherein a reading margin can be allowed a large value as current/voltage characteristics in FIG. 4 show, wrong reading is reduced and high reliability is acquired can be provided.
Also, as the capacitor is composed by the floating-gate extended on the element isolation insulating film in addition to the effect described above in the second aspect of the invention, the structure described above can be realized without increasing the area of one cell.
Also, a third aspect of the invention is characterized in that a gate electrode is connected to a word line, a source area is connected to a source line, a drain area is connected to a drain line, a semiconductor substrate is composed so that it is isolated every column and voltage can be independently applied, is connected to a back gate line so that source line potential and drain line potential can be respectively set to floating potential or ground potential every line and column, a depletion layer spreads in the channel area of a ferroelectric transistor composing an unselected cell in the vicinity of a selected cell by keeping the source/drain potential a desired value and an inversion layer is prevented from being formed when data is written to the selected cell in a nonvolatile memory wherein ferroelectric transistors composed by laminating a gate electrode via at least a first ferroelectric layer on the surface between a source area and a drain area respectively formed on a semiconductor substrate are arrayed in the matrix.
A fourth aspect of the invention is characterized in that a depletion layer spreads in the channel area of a ferroelectric transistor in an unselected cell by making one of the source and the drain of a selected cell ground potential, making the source/drain potential of an unselected cell on at least an adjacent line of the selected cell floating and keeping the source/drain potential a desired value and drain current is prevented when data is written of the selected cell in a nonvolatile memory wherein ferroelectric transistors composed by laminating a gate electrode via at least a first ferroelectric layer on the surface between a source area and a drain area respectively formed on a semiconductor substrate are arrayed in the matrix, the gate electrode is connected to a word line, the source area is connected to a source line, the drain area is connected to a drain line, the semiconductor substrate is isolated every column so that voltage can be independently applied, is connected to a back gate line and source line potential and drain line potential can be respectively set to floating potential or ground potential every line and column.
In such an MFMIS transistor, as an equivalent circuit diagram in FIG. 16 shows, a capacitor Cf depending upon the ferroelectric film 7, a capacitor COX depending upon the gate oxide film 5 and a capacitor CD depending upon the depletion layer are connected in series. Therefore, in case voltage V is applied between the substrate 1 and the control gate 8, the voltage is divided into Vf, VOX and VD as shown in the following expression (1).
V=VF+VOX+VD
CFVF=COXVOX=CDVDxe2x88x92qxe2x80x83xe2x80x83(1)
q: Quantity of charge generated by capacitor
Therefore, potential voltage Vf shown in the following expression is applied to the capacitor Cf depending upon the ferroelectric film 7.
VF=CFCOXCD/(CFCOX+COXCD+CDCF).VGxe2x80x83xe2x80x83(2)
Therefore, when the source and the drain are in a floating state, a depletion layer spreads as shown in FIG. 9A and the capacity CD of the depletion layer is increased. Therefore, voltage VF applied to the ferroelectrics is as follows and VF is reduced.
VF={CFCOXCD/(CFCOX+COXCD+CDCF)}.VGxe2x80x83xe2x80x83(A)
Therefore, when this state is used for an unselected cell, disturbance for the unselected cell is reduced.
In the meantime, as an electron is supplied from the source/drain areas to the channel area as shown in FIG. 9B and an inversion layer is generated when the source and the drain are grounded, voltage VF applied to the ferroelectrics is as follows.
VF{CFCOX/(CF+COX) }.VGxe2x80x83xe2x80x83(B) 
Then, in the invention, for a selected cell which is a writing cell, sufficient voltage VF is applied to the ferroelectric film, while for an adjacent cell, the source and the drain are made floating, the depletion layer is made spread in the channel area of FET, voltage VF applied to the ferroelectrics is reduced by increasing the capacity of the depletion layer and wrong written is prevented so that a state shown in FIG. 9A is realized.
Concretely, for a cell having potential difference between the word line and the back gate line except a selected cell, its potential is set so that potential at the source equivalent to a line and at the drain equivalent to a column is prevented from being both zero, all unselected cells are made a state shown in FIG. 9B, voltage applied to the ferroelectrics is reduced by potential applied to the selected cell and disturbance is prevented.